1. Field of the Invention
The invention related to a semiconductor device and a manufacturing technology of the same, particularly, relates to a technology which is effective when applied to manufacture of a semiconductor device including a nonvolatile memory and peripheral circuits thereof.
2. Description of the Related Art
As a kind of nonvolatile memory (Electrically Erasable and Programmable Read Only Memory) which can electrically rewrite data, a split-gate type memory cell structure using a charge storage layer including an ONO (Oxide Nitride Oxide) film is known.
As peripheral circuits of the nonvolatile memory, for example, circuits including a low withstand voltage MISFET such as a sense amplifier, a column decoder and a row decoder, and circuits including and a high withstand voltage MISFET such as a boosting circuit are known.
In Japanese Patent Application Laid-open No. 2006-019373 (Patent Document 1), a technology in a split-gate type MONOS nonvolatile memory including a control gate and a memory gate is disclosed, in which the memory gate includes a doped polycrystalline silicon film and the control gate includes a polycrystalline silicon film which is formed by ion-implanting an impurity into an undoped silicon film. In the above Patent Document 1, in addition to the MONOS-type nonvolatile memory, a low withstand voltage and a high withstand voltage MISFET which are included in peripheral circuits thereof are disclosed.
In addition, in Japanese Patent Application Laid-open No. 2003-218232 (Patent Document 2), in a semiconductor device including a low withstand voltage and a high withstand voltage MOSFET, a structure is disclosed, in which a film thickness (height) of a gate electrode of the low withstand voltage MOSFET differs from a film thickness (height) of a gate electrode of the high withstand voltage MOSFET.
A semiconductor device considered by the inventors includes, for example, a split-gate type memory cell including a control transistor and a memory transistor, such as one written in Japanese Patent Application Laid-open No. 2006-019373 (Patent Document 1), and a low withstand voltage and a high withstand voltage MISFET included in peripheral circuits thereof. FIG. 21 is a cross-sectional view schematically showing relevant parts of the semiconductor device considered by the inventors. In FIG. 21, a memory cell MC0 is shown at a memory array region, a low withstand voltage MISFET (Q10) is shown at a low withstand voltage MIS region in a peripheral circuit region, and a high withstand voltage MISFET (Q20) is shown at a high withstand voltage MIS region in the peripheral circuit region.
As shown in FIG. 21, the memory cell MC0 includes a control gate 8, a gate insulating film 6, a charge storage layer 16, a memory gate 9, and a sidewall spacer 12, n−type semiconductor regions 11d, 11s and n+type semiconductor regions 10d, 10s. The control gate 8 and the memory gate 9 form a split gate.
In the memory cell MC0, the control gate 8 is formed over a p-type well 2 in a principal surface of a semiconductor substrate 1 (hereinafter, referred to as a “substrate”) made of a p-type single crystalline silicon substrate or the like through the gate insulating film 6. One part of the charge storage layer 16 is formed at one sidewall of the control gate 8 and the other part thereof is formed over the p-type well 2. The charge transfer layer 16 is an ONO (Oxide Nitride Oxide) film including two layers of silicon oxide films and a silicon nitride film sandwiched therebetween.
The memory gate 9 is formed at one sidewall of the control gate 8 and electrically separated from the control gate 8 through one part of the charge storage layer 16 as well as electrically separated from the p-type well 2 through the other part of the charge storage layer 16. The sidewall spacer 12 is formed at the other sidewall of the control gate 8 and at one sidewall of the memory gate 9, namely, it is the sidewall spacer of the split gate.
The n−type semiconductor region 11d is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the control gate 8. The n+type semiconductor region 10d which has higher impurity concentration than the n−type semiconductor region 11d is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the side wall spacer 12 at the side of the control gate 8. Additionally, the n−type semiconductor region 11s is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the memory gate 9. The n+type semiconductor region 10s which has higher impurity concentration than the n−type semiconductor region 11s is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the sidewall spacer 12 at the side of the memory gate 9.
The low withstand voltage MISFET (Q10) forming the peripheral circuit of the memory cell MC0 includes a gate electrode 14, the gate insulating film 6, the sidewall spacer 12, an n−type semiconductor region 17 and an n+type semiconductor region 26. The n−type semiconductor region 17 is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the gate electrode 14. The n+type semiconductor region 26 is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the sidewall spacer 12.
The high withstand voltage MISFET (Q20) forming the peripheral circuit of the memory cell MC0 includes a gate electrode 15, a gate insulating film 7, the sidewall spacer 12, an n−type semiconductor region 24 and an n+type semiconductor region 27. The n−type semiconductor region 24 is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the gate electrode 15. The n+type semiconductor region 27 is formed over the surface of the p-type well 2, one end of which is arranged in the vicinity of the sidewall spacer 12.
A manufacturing technology of forming the control gate 8 of the memory cell MCO, the gate electrode 14 of the low withstand voltage MISFET (Q10), the gate electrode 15 of the high withstand voltage MISFET (Q20) is explained with reference to FIG. 22. FIG. 22 is a cross-sectional view schematically showing relevant parts of the semiconductor device considered by the inventors in a manufacturing process.
As shown in FIG. 22, the gate insulating films 6 and 7 made of a silicon oxide film or the like are formed over the surface of the p-type well 2 by thermally oxidizing the substrate 1 made of the silicon substrate or the like. Next, an electrode material film 8A made of an undoped silicon film or the like having a film thickness of approximately 250 nm is deposited over the substrate 1 by a CVD method. After that, ion implantation of an impurity (for example, phosphorous or arsenic) is performed to the electrode material film 8A which is the undoped silicon film to change the updoped silicon film into an n-type silicon film. The control gate 8 of the memory cell MC0, the gate electrode 14 of the low withstand voltage MISFET (Q10) and the gate electrode 15 of the high withstand voltage MISFET (Q20) are formed from the electrode material film 8A (refer to FIG. 21).
The gate electrode film 6 is formed at the memory array region and the low withstand voltage MIS region, and the gate insulating film 7 is formed at the high withstand voltage MIS region. That is, the gate insulating film 6 at the memory array region and the gate insulating film 6 at the low withstand voltage MIS region are the same film formed in the same process. The gate insulating film 7 is formed thicker in a film thickness (approximately 7 to 8 nm) than a film thickness of the gate insulating film 6 (approximately 3 to 4 nm) for securing withstand voltage. The electrode material film 8A is formed at the memory array region, the low withstand voltage MIS region and the high withstand voltage MIS region. That is, the electrode material films 8A in these regions are the same film formed in the same process.
The reason why the gate insulating film 6 under the control gate 8 and the gate electrode 14 is thinner than the gate insulating film 7 under the gate insulating film 15 is for operating transistors at high speed. The reason why the gate insulating film 7 under the gate electrode 15 is thicker than the gate insulating film 6 under the control gate 8 and the gate electrode 14 is for preventing dielectric breakdown even when high withstand voltage is applied.
It is necessary to make the gate electrode thinner in a film thickness as the gate electrode (gate length) is miniaturized, for securing the ratio (aspect ratio) of height (thickness) of the gate electrode for the gate length. In the semiconductor device considered by the inventors, the electrode material film 8A forming the control gate 8 of the memory cell MC0, the gate electrode 14 of the low withstand voltage MISFET (Q10) and the gate electrode 15 of the high withstand voltage MISFET (Q20) is formed in the same process, therefore, when the gate electrode is manufactured to be miniaturized (after the 90 nm generation), the whole electrode material film 8A is made to be thin in the film thickness. Therefore, for example, when the n−type semiconductor region 24 and an n+type semiconductor region 27 of the high withstand voltage MISFET (Q20) are formed, it is concerned that ions break through the gate electrode 15 (electrode material film 8A) of the high withstand voltage MISFET (Q20) which has been made thin, which causes deterioration and variations of characteristics of the high withstand voltage MISFET (Q20), lowering of reliability of the gate insulating film 7, lowering of hot carrier resistance and the like.
Consequently, as described in the Patent Document 2, it is considered that, in the high withstand voltage MISFET (Q20) as against the low withstand voltage MISFET (Q10), the gate electrode 15 which is thicker than the gate electrode 14 is formed, thereby preventing the implanted ions from breaking through the gate electrode 15 when forming the n−type semiconductor region 24 and the n+type semiconductor region 27. However, since the low withstand voltage MISFET (Q10) and the high withstand voltage MISFET (Q20) are semiconductor elements forming peripheral circuits of the memory cell MC0, it is concerned that deterioration of characteristics of the memory cell MC0 is caused by merely changing the film thickness of the gate electrode 14 with respect to the gate electrode 15.
For example, when the film thickness of the control gate 8 at the memory cell MC0 is made thin as the gate electrode (gate length) is miniaturized, there is a case in which the sidewall spacer 12 of the split gate does not function as a spacer. The sidewall spacer 12 is formed by etching back (anisotropic etching) an silicon oxide film deposited over the substrate 1 by the CVD method so as to cover the split gate including the control gate 8 and the memory gate 9. Consequently, the size (width) of the lower side of the sidewall spacer 12 in the gate-length direction along the substrate 1 is limited by the height of the split gate, that is, the thickness of the control gate 8, therefore, when the film thickness of the control gate 8 is made thin, there is a case that it is difficult to secure the width of the sidewall spacer 12 sufficiently. Accordingly, it is concerned that a problem of occurrence of junction leakage between the n+type semiconductor regions 10d, 10s formed by ion-implanting an impurity, using the split gate and the sidewall spacer 12 as masks, and the p-type well 2 forming the junction surface.